Hyper-threading

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Hyper-threading, officially called Hyper-Threading Technology (HTT), is Intel's trademark for their implementation of the simultaneous multithreading technology on the Pentium 4 microarchitecture. It is a more advanced form of Super-threading that debuted in U.S. patent 4,847,755 (Gordon Morrison, et. al) and can be seen in use on the Intel Xeon processors and was later added to Pentium 4 processors. The technology improves processor performance under certain workloads by providing useful work for execution units that would otherwise be idle, for example during a cache miss. A Pentium 4 with Hyper-Threading enabled is treated by the operating system as two processors instead of one.

1 Performance
2 Details
3 Security
4 Future
5 See also
6 References
7 External links
8 Sources

The advantages of Hyper-Threading are listed as: improved support for multi-threaded code, allowing multiple threads to run simultaneously, improved reaction and response time.

According to Intel, the first implementation only used an additional 5% of the die area over the comparable non-hyperthreaded processor, yet yielded performance improvements of 15–30%.

Intel claims up to a 30% speed improvement compared against an otherwise identical, non-simultaneous multithreading Pentium 4. The performance improvement seen is very application-dependent, however, and some programs actually slow down slightly when Hyper Threading Technology is turned on. This is due to the replay system of the Pentium 4 tying up valuable execution resources, thereby starving the other thread. (The Pentium 4 Prescott core gained a replay queue, which reduces execution time needed for the replay system, but this is not enough to completely overcome the performance hit.) However, any performance degradation is unique to the Pentium 4 (due to various architectural nuances), and is not characteristic of simultaneous multithreading in general.

Hyper-Threading works by duplicating certain sections of the processor—those that store the architectural state—but not duplicating the main execution resources. This allows a Hyper-Threading equipped processor to pretend to be two "logical" processors to the host operating system, allowing the operating system to schedule two threads or processes simultaneously. Where execution resources in a non-Hyper-Threading capable processor are not used by the current task, and especially when the processor is stalled, a Hyper-Threading equipped processor may use those execution resources to execute another scheduled task. (The processor may stall due to a cache miss, branch misprediction, or data dependency.)

Except for its performance implications, this innovation is transparent to operating systems and programs. All that is required to take advantage of Hyper-Threading is symmetric multiprocessing (SMP) support in the operating system, as the logical processors appear as standard separate processors.

However, it is possible to optimize operating system behavior on Hyper-Threading capable systems, such as the Linux techniques discussed in Kernel Traffic. For example, consider an SMP system with two physical processors that are both Hyper-Threaded (for a total of four logical processors). If the operating system's process scheduler is unaware of Hyper-Threading, it would treat all four processors the same. As a result, if only two processes are eligible to run, it might choose to schedule those processes on the two logical processors that happen to belong to one of the physical processors. Thus, one CPU would be extremely busy while the other CPU would be completely idle, leading to poor overall performance. This problem can be avoided by improving the scheduler to treat logical processors differently from physical processors; in a sense, this is a limited form of the scheduler changes that are required for NUMA systems.

In May 2005 Colin Percival presented a paper, Cache Missing for Fun and Profit (PDF file), demonstrating that a malicious thread operating with limited privileges can monitor the execution of another thread through their influence on a shared data cache, allowing for the theft of cryptographic keys. Note that while the attack described in the paper was demonstrated on an Intel Pentium 4 with HyperThreading processor, the same techniques could theoretically apply to any system where caches are shared between two or more non-mutually-trusted execution threads; see also side channel attack.

Older Pentium 4 based CPUs use Hyper-Threading, but the current-generation Pentium M based cores, Merom, Conroe, and Woodcrest, do not. Hyper-Threading is a specialized form of simultaneous multithreading (SMT), which has been said to be on Intel's plans for the generation after Merom, Conroe and Woodcrest.

More recently Hyper-Threading has been criticised as being energy inefficient. For example, specialist low power CPU design company ARM has stated SMT can use up to 46% more power than dual CPU designs. Furthermore, they claim SMT increases cache thrashing by 42%, whereas dual core results in a 37% decrease[1]. These considerations are claimed to be the reason Intel dropped SMT from the following microarchitecture.

However, for 2008 Intel has claimed that the upcoming Nehalem will see the return of Hyper-Threading. Nehalem is projected to contain up to 8 cores and will be able to effectively scale 16+ threads.^[1]