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An instruction cycle (also called fetch-and-execute cycle, fetch-decode-execute cycle (FDX) is the time period during which a computer reads and processes a machine language instruction from its memory or the sequence of actions that the central processing unit (CPU) performs to execute each machine code instruction in a program.

The name fetch-and-execute cycle is commonly used. The instruction must be fetched from main memory, and then executed by the CPU. This is fundamentally how a computer operates, with its CPU reading and executing a series of instructions written in its machine language. From this arise all functions of a computer familiar from the user's end.

Contents 1 Instruction cycle 1.1 Fetch the instruction from main memory 1.2 Decode the instruction 1.3 Registers that are critical to the fetch-execute cycle 1.4 Fetch data from main memory 1.5 Execute the instruction 1.6 Store results 2 Fetch cycle 3 Execute cycle 4 The Fetch-Execute cycle in Transfer Notation

Each computer's CPU can have different cycles based on different instruction sets.

The CPU presents the value of the program counter (PC) on the address bus. The CPU then fetches the instruction from main memory via the data bus into the Memory Data Register (MDR). The value from the MDR is then placed into the Current Instruction Register (CIR), a circuit that holds the instruction so that it can be decoded and executed.

The instruction decoder interprets and implements the instruction.

The instruction register (IR) - holds the current instruction. The program counter (PC) - holds the address in memory of the next instruction to be executed.

Read the effective address from main memory if the instruction has an indirect address. Fetch required data from main memory to be processed and placed into registers.

From the instruction register, the data forming the instruction is decoded by the control unit. It then passes the decoded information as a sequence of control signals to the relevant function units of the CPU to perform the actions required by the instruction such as reading values from registers, passing them to the Arithmetic logic unit (ALU) to add them together and writing the result back to a register. A condition signal is sent back to the control unit by the ALU if it is involved.

The result generated by the operation is stored in the main memory, or sent to an output device. Based on the condition feedback from the ALU, the PC is either incremented to address the next instruction or updated to a different address where the next instruction will be fetched. The cycle is then repeated.

Steps 1 and 2 of the Instruction Cycle are called the Fetch Cycle. These steps are the same for each instruction. The fetch cycle processes the instruction from the instruction word which contains an opcode and an operand.

Steps 3 and 4 of the Instruction Cycle are part of the Execute Cycle. These steps will change with each instruction.

The first step of the execute cycle is the Process-Memory. Data is transferred between the CPU and the I/O module. Next is the Data-Processing uses mathematical operations as well as logical operations in reference to data. Central alterations is the next step, is a sequence of operations, for example a jump operation. The last step is a combined operation from all the other steps.

MAR<-[PC]

MDR<-[MemoryLocation]

PC<-[PC]+1

IR<-[MDR]