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OpenCores
From Wikipedia, the free encyclopedia
OpenCores is a loose community of people who are interested in developing digital open source hardware through electronic design automation, with a similar ethos to the free software movement and the open source movement. OpenCores hope to eliminate redundant design work and slash development costs.
The components produced by the OpenCores initiative use several different software licenses, but the most common is GNU LGPL, which states that any modifications to a component must be shared with the community, while you can still use it together with proprietary components.
The library will consist of design elements from processors, memory controllers, peripherals, motherboards, and other components. Emerging semicon manufacturers could use the information and license designs for free.
Currently the emphasis is on digital modules called 'cores', commonly known as IP Cores. The components are used for creating both custom integrated circuits (ASICs) and FPGAs.
The cores are implemented in the hardware description languages Verilog, VHDL or SystemC which may be synthesized to either silicon or grid arrays.
The project aims at using a common non-proprietary system bus named Wishbone, and most components are nowadays adapted to this bus.
Among the components created by OpenCores contributors are:
- OpenRISC - a highly configurable RISC central processing unit
- A Zilog Z80 clone
- USB 2.0 controller
- Tri Ethernet controller, 10/100/1000 Mbit
- Encryption units, for example DES, AES & RSA
- HyperTransport Tunnel
- A PIC16F84 core