From Wikipedia, the free encyclopedia

Power Architecture CPU architecture
Historical
POWER • PPC6xx • PowerPC-AS • POWER2 • POWER3 • POWER4
Current
PowerPC • e200 • e600 • PA6T • POWER5 • PPC970 • Cell PPE
Future
POWER6 • POWER7 • e700
Related Links
RISC • AltiVec • IBM System p • IBM System i • Playstation 3 • Xbox 360

PWRficient is the name of a series of microprocessors designed by P.A. Semi.

PWRficient are 64-bit Power Architecture processors, designed for high performance and extreme power efficieancy. The processor are highly modular and can be combined to multi-core system-on-a-chip designs, combining CPU, northbridge and southbridge functionality on a single processor die.

The PA6T is the first processor core from P.A. Semi, and they are offered in two distinct lines of products, 16xxM dual core processors and 13xxM/E single core processors. The different parts in the refective lines differ in regards to amount of L2 cache, memory controllers, communication functionality and cryptography offloading features. In the future P.A. Semi plan to offer parts with up to 16 cores.

The PA6T core is the first Power Architecture core to be designed from scratch outside the AIM alliance (ie it's not designed by either IBM, Motorola/Freescale or Apple Computer) in ten years. Since Texas Instruments is one of the investors in P.A. Semi it is suggested that their fabrication plants will be used to manufacture the PWRficient processors.^[1]

PWRficient processors are currently shipping to select customers and are set to be released for world wide sale sale in Q4 2007.^[2]

Contents 1 Implementation 1.1 CPU 1.2 Memory system 1.3 I/O 2 Links 3 References

PWRficient processors comprise of three parts

PA6T

• Superscalar, out-of-order 32/64 bit Power Architecture processor core.
• Adheres to the Power ISA v.2.04
• Little/big endian operation
• 64/64 kB instruction and data L1 caches. 32 GB/s bandwidth.
• 6 execution units including a double precision FPU and Altivec unit.
• Hypervisor and Virtualization support.
• max 7W at 2 GHz
• 11 million transistors, 10 mm² large @ 65 nm.

CONEXIUM

• scalable cross-bar interconnect
• 1-8 SMP cores
• 1-2 L2 caches, 512 kB - 8 MB large. 16 GB/s bandwidth.
• 1-4 1067 MHz DDR2 memory controllers. 16 GB/s bandwidth.
• 64 GB/s peak bandwidth.
• MOESI coherency

ENVOI

• Centralized DMA engine, 32 GB/s bandwidth
• 16-64 SerDes lanes
• XAUI
• PCI Express
• SGMII
• Offload engine for cryptography, RAID, TCP

• P.A. Semi homepage
• Start-up plans new energy-efficient processor
• PA Semi attacks performance/Watt

1. ^ PA Semi heads to 16 cores on back of $50m boost. The Register. Retrieved on October 17, 2006.
2. ^ Press release. P.A. Semi. Retrieved on February 7, 2007.

FPF 2005: P.A. Semi's PA6T-1682M System on a Chip – Real World Technologies