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Sign extension
From Wikipedia, the free encyclopedia
Sign extension is the operation, in computer arithmetic, of increasing the number of bits of a binary number while preserving the number's sign (positive/negative). This is done by appending digits to the most significant side of the number, following a procedure dependent on the particular signed number representation used.
For example, if six bits are used to represent the number +10 (binary: 001010) and the sign extend operation increases the word length to 16 bits, then the new representation is simply 0000 0000 0000 1010 (assuming the left side is the most significant bit). Thus, the fact that the original value was positive is still maintained. If ten bits are used to represent the value -15 using two's complement (11 1111 0001), and again sign extend to 16 is used, the new representation would be 1111 1111 1111 0001. Thus, by padding the left side with ones, the negativeness of the original number is maintained.
In the x86 instruction set used by the main microprocessors of all common PCs, sign extension is done by the instructions cbw, cwd, cwde, and cdq ("convert byte to word", "c. word to doubleword", "c. w. to extended dw.", and "c. dw. to quadword", respectively; in the x86 context, a byte has 8 bits, a word 16 bits, a doubleword and extended doubleword 32 bits, and a quadword 64 bits).
- Mano, Morris M.; Kime, Charles R. (2004). Logic and Computer Design Fundamentals (3rd ed.), pp 453. Pearson Prentice Hall. ISBN 0-13-140539-X.