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In parallel computing, speedup refers to how much a parallel algorithm is faster than a corresponding sequential algorithm.

Speedup is defined by the following formula:

where:

• p is the number of processors
• T₁ is the execution time of the sequential algorithm
• T_p is the execution time of the parallel algorithm with p processors

Linear speedup or ideal speedup is obtained when . When running an algorithm with linear speedup, doubling the number of processors doubles the speed. As this is ideal, it is considered very good scalability.

Efficiency is a performance metric defined as . It is a value, typically between zero and one, estimating how well-utilized the processors are in solving the problem, compared to how much effort is wasted in communication and synchronization. Algorithms with linear speedup and algorithms running on a single processor have an efficiency of 1, while many difficult-to-parallelize algorithms have efficiency such as that approaches zero as the number of processors increases.

Sometimes a speedup of more than N when using N processors is observed in parallel computing, which is called super linear speedup. Super linear speedup rarely happens and often confuses beginners, who believe the theoretical maximum speedup should be N when N processors are used.

One possible reason for a super linear speedup is the cache effect resulting from the different memory hierarchies of a modern computer: In parallel computing, not only the numbers of processors change, so does the size of accumulated caches from different processors. With the larger accumulated cache size, more or even all core data set can fit into caches and the memory access time reduces dramatically, which causes the extra speedup in addition to that from the actual computation.

Super linear speedups can also occur when performing Backtracking in parallel: One thread can prune a branch of the exhaustive search that another thread would have taken otherwise.

• Amdahl's law
• Gustafson's law
• Karp-Flatt Metric
• Scalability
• Brooks's law

Glen L. Beane, "The effects of Microprocessor Architecture on Speedup in Distributed Memory Supercomputers" (M.S. thesis, The University of Maine, 2004) http://www.umcs.maine.edu/~beaneg/docs/thesis.pdf

v • d • e Parallel computing topics
General	High-performance computing
Parallelism	Bit-level parallelism · Instruction level parallelism · Data parallelism · Task parallelism
Theory	Speedup · Amdahl's law · Flynn's taxonomy (SISD • SIMD • MISD • MIMD) · Cost efficiency · Gustafson's law · Karp-Flatt metric
Elements	Process · Thread · Fiber · Parallel Random Access Machine
Coordination	Multiprocessing · Multithreading · Multitasking · Memory coherency · Cache coherency · Barrier · Synchronization · Distributed computing · Grid computing
Programming	Programming model · Implicit parallelism · Explicit parallelism
Hardware	Computer cluster · Beowulf · Symmetric multiprocessing · Non-Uniform Memory Access · Cache only memory architecture · Asymmetric multiprocessing · Simultaneous multithreading · Shared memory · Distributed memory · Massively parallel processing · Superscalar processing · Vector processing · Supercomputer · Stream processing · GPGPU
Software	Distributed shared memory  · Application checkpointing · Warewulf
APIs	POSIX Threads · OpenMP · Message Passing Interface (MPI)
Problems	Embarrassingly parallel · Grand Challenge · Software lockout