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SSE (Streaming SIMD Extensions, originally called ISSE, Internet Streaming SIMD Extensions) is a SIMD (Single Instruction, Multiple Data) instruction set designed by Intel and introduced in 1999 in their Pentium III series processors as a reply to AMD's 3DNow! (which had debuted a year earlier). The fully expanded abbreviation stands for "Streaming Single Instruction, Multiple Data Extensions".

SSE contains 70 new instructions.

It was originally known as KNI for Katmai New Instructions (Katmai was the code name for the first Pentium III core revision). During the Katmai project Intel was looking to distinguish it from their earlier product line, particularly their flagship Pentium II. AMD eventually added support for SSE instructions, starting with its Athlon XP processor.

Intel was generally disappointed with their first IA-32 SIMD effort, MMX. MMX had two main problems: it re-used existing floating point registers making the CPU unable to work on both floating point and SIMD data at the same time, and it only worked on integers.

SSE originally added eight new 128-bit registers known as XMM0 through XMM7. The x64 extensions from both Intel and AMD add a further eight registers XMM8 through XMM15. There is also a new 32-bit control / status register, MXCSR.

Each register packs together four 32-bit single-precision floating point numbers. Integer SIMD operations may still be performed with the eight 64-bit MMX registers.

Because these 128-bit registers are additional program states that the operating system must preserve across task switches, they are disabled by default until the operating system explicitly enables them. This means that the OS must know how to use the FXSAVE and FXRSTOR instructions, which is the extended pair of instructions which can save all x87 and SSE register states all at once. This support was quickly added to all major IA-32 operating systems.

Because SSE adds floating point support, it sees much more use than MMX. The addition of SSE2's integer support makes SSE even more flexible. While MMX is redundant, operations can be operated in parallel with SSE operations offering further performance increases in some situations.

The first CPU to support SSE, the Pentium III, shared execution resources between SSE and the FPU. While a compiled application can interleave FPU and SSE instructions side-by-side, the Pentium III will not issue a FPU and a SSE instruction in the same clock-cycle. This limitation reduces the effectiveness of pipelining, but the separate XMM registers do allow SIMD and scalar floating point operations to be mixed without the performance hit from explicit MMX/floating point mode switching.

Contents 1 SSE Instructions 2 Example 3 Later versions 4 References 5 See also

• SSE introduced both scalar and packed floating point instructions.

Floating point instructions

• Memory-to-Register / Register-to-Memory / Register-to-Register data movement

   *Scalar - MOVSS
   *Packed - MOVAPS, MOVUPS, MOVLPS, MOVHPS, MOVLHPS, MOVHLPS

• Arithmetic

   *Scalar - ADDSS, SUBSS, MULSS, DIVSS, RCPSS, SQRTSS, MAXSS, MINSS, RSQRTSS 
   *Packed - ADDPS, SUBPS, MULPS, DIVPS, RCPPS, SQRTPS, MAXPS, MINPS, RSQRTPS

• Compare

   *Scalar - CMPSS, COMISS, UCOMISS 
   *Packed - CMPPS

• Data shuffle and unpacking

   *Packed - SHUFPS, UNPCKHPS, UNPCKLPS

• Data-type conversion

   *Scalar - CVTSI2SS, CVTSS2SI, CVTTSS2SI
   *Packed - CVTPI2PS, CVTPS2PI, CVTTPS2PI  

• Bitwise logical operations

   *Packed - ANDPS, ORPS, XORPS, ANDNPS

Integer instructions

• Arithmetic

   *PMULHUW, PSADBW, PAVGB, PAVGW, PMAXUB, PMINUB, PMAXSW, PMINSW

• Data movement

   *PEXTRW, PINSRW

• Other

   *PMOVMSKB, PSHUFW

Other instructions

• MXCSR management

   *LDMXCSR, STMXCSR

• Cache and Memory management

   *MOVNTQ, MOVNTPS, MASKMOVQ, PREFETCH0, PREFETCH1, PREFETCH2, PREFETCHNTA, SFENCE

The following simple example demonstrates the advantage of using SSE. Consider an operation like vector addition, which is used very often in computer graphics applications. To add two single precision, 4-component vectors together using x87 requires four floating point addition instructions

vec_res.x = v1.x + v2.x;
vec_res.y = v1.y + v2.y;
vec_res.z = v1.z + v2.z;
vec_res.w = v1.w + v2.w;

This would correspond to four x87 FADD instructions in the object code. On the other hand, as the following pseudo-code shows, a single 128 bit 'packed-add' instruction can replace the four scalar addition instructions.

movaps xmm0,address-of-v1          ;xmm0=v1.w | v1.z | v1.y | v1.x 
addps xmm0,address-of-v2           ;xmm0=v1.w+v2.w | v1.z+v2.z | v1.y+v2.y | v1.x+v2.x               
movaps address-of-vec_res,xmm0 

• SSE2, introduced with the Pentium 4, is a major enhancement to SSE (which some programmers renamed "SSE1"). SSE2 adds new math instructions for double-precision (64-bit) floating point and also extends MMX instructions to operate on 128-bit XMM registers. Until SSE4 [see below], SSE integer instructions introduced with later SSE extensions would still operate on 64-bit MMX registers because the new XMM registers require operating system support. SSE2 enables the programmer to perform SIMD math of virtually any type (from 8-bit integer to 64-bit float) entirely with the XMM vector-register file, without the need to touch the (legacy) MMX/FPU registers. Many programmers consider SSE2 to be "everything SSE should have been", as SSE2 offers an orthogonal set of instructions for dealing with common datatypes.

• SSE3 called Prescott New Instructions, is an incremental upgrade to SSE2, adding a handful of DSP-oriented mathematics instructions and some process (thread) management instructions.

• SSSE3 is an incremental upgrade to SSE3, adding 16 new opcodes which include permuting the bytes in a word, multiplying 16-bit fixed-point numbers with correct rounding, and within-word accumulate instructions. SSSE3 is often mistaken for SSE4 as this term was used during the development of the Core microarchitecture.

• SSE4 is another major enhancement, adding a dot product instruction, lots of additional integer instructions, a popcnt instruction, and more. SSE4 ends MMX register support. No processors on the market officially support SSE4, however SSE4 will be supported on 'Penryn' a version of the Core 2 microarchitecture^[1]. An overview can be found at http://www.intel.com/technology/architecture-silicon/sse4-instructions/index.htm .
• SSE5 is a new iteration announced by AMD in August 2007^[2][3]

• Assembly Language
• MMX
• 3DNow!
• AltiVec
• Pentium III's SSE implementation