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Source-synchronous
From Wikipedia, the free encyclopedia
Source-Synchronous clocking refers to the technique of sourcing a clock along with the data. Specifically, the timing of unidirectional data signals is referenced to a clock sourced by the same device that generates those signals, and not to a global clock (i.e. generated by a bus master).
This type of clocking is common in high-speed interfaces, including DDR SDRAM interfaces, SGI XIO interface, HyperTransport, SPI-4.2 and many others.
A reason that source-synchronous clocking is useful is that it has been observed that all of the gates within a given semiconductor device experience roughly the same process-voltage-temperature (PVT) variation. This means delay experienced by the data through a device tracks the delay experienced by the clock through that same device over PVT. This advantage allows higher speed operation as compared to the traditional technique of providing the clock from a third device to both the transmitter and the receiver. Another benefit is that higher complexity data-recovery or clock-data-recovery circuits are not required when this technique is used.
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